A SIL Verification assessment is typically carried out following a SIL Determination study, to verify that the SIFs, which have been (typically) identified as part of a Layers of Protection Analysis (LOPA), meet their targeted SIL level.

Velimor is recognized as a SIL Verification consultancy and has extensive experience of carrying out SIL Verification studies to address random hardware failures and minimum architecture in terms of hardware fault tolerance (HFT) for the SIFs under consideration as per the requirements specified in IEC 61508 / IEC 61511.

Our SIL Verification consultants can also provide plant reliability, availability and maintainability (RAMS) studies using similar techniques

Velimor can provide:

• An assessment of the random hardware reliability, and minimum architecture in terms of Hardware Fault Tolerance (HFT) of each SIF, comprising input devices, logic modules, actuator and final element devices;
• SIL Verification assessments of proposed or existing SIFs conducted using failure rate data provided by the client / vendor, or from Velimor's very own failure rate database. This can be used to confirm, or otherwise, hardware reliability and compliance with safety requirements parameters such as Probability of Failure on Demand (PFD) and frequency of a dangerous failure (PFH);
• Sensitivity analyses to optimize proof test and automatic test intervals;
• Use of software package, ProSET®, offering accuracy and consistency throughout the SIL Verification assessment;
• Recommendations for SIF modifications where the SIL Verification assessment has shown that the SIL target cannot be met, detailing the improvement options that will allow the target to be met;
• Documentation of the assessment process, providing a visible and traceable analysis in a formal report;
• Development of proof testing procedures to ensure that the proof test for the SIFs are carried out at the required intervals by competent personnel to ensure an accurate and consistent approach.